The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the same, and, more particularly, to a technique which is effective when applied to a semiconductor integrated circuit device having a memory cell wherein the capacitor insulating film of a capacitive element (capacitor) is made of a highly dielectric material.
In a large capacity DRAM (Dynamic Random Access Memory) of the type available in recent years, in order to compensate for the reduction in the accumulated charge of a capacitive element, resulting from the miniaturization of a memory cell, there has been adopted a stacked capacitor structure in which the capacitive element is arranged over a memory cell selecting MISFET. Moreover, the surface area of the capacitive element is enlarged by forming its lower electrode (storage electrode) into a fin shape or a cylindrical shape, and the capacitor insulating film is made of a material having a high dielectric constant. Especially, a tantalum oxide (Ta.sub.2 O.sub.5) representative of the one of highly dielectric materials has a dielectric constant as high as 20 to 25 and has a high matching characteristic with the DRAM process of the prior art, so that the application of the DRAM to the capacitive element is being more widely employed.
When the capacitor insulating film of the capacitive element is made of tantalum oxide, a material for preventing the deterioration of the film quality of the tantalum oxide has to be selected as the material of the upper electrode (or plate electrode) to be formed over the capacitor insulating film. This upper electrode material may be suitably exemplified by a refractory metal, such as W (tungsten), Pt (platinum) or Mo (molybdenum) or its nitride, such as TiN (titanium nitride).
According to "Jpn. J. Appl. Phys. Vol. 33 (1994) Pt. 1, No. 3A", having investigated the influences of the leakage current upon the tantalum oxide film before and after the annealing step of the electrode material, it has been reported, based on experimental results, that the electric characteristics of the tantalum oxide film are determined by the work function of the electrode material and the stability of the interface between the upper electrode and the tantalum oxide, and that the most appropriate material is TiN for the annealing at a low temperature (about 400.degree. C.) and Mo or MoN (molybdenum nitride) for the annealing at a high temperature (about 800.degree. C.).
Since the lower electrode of the capacitive element of the DRAM has a complicated surface shape, as described above, the CVD (Chemical Vapor Deposition) method having an excellent step coverage has to be used rather than the sputtering method when a tantalum oxide film is deposited over the lower electrode. However, the tantalum oxide film deposited by the CVD method has to be annealed, after being formed, at a temperature as high as about 700 to 800.degree. C. because a desired dielectric constant cannot achieved as it is. With this annealing, however, an oxide film is formed at the interface with the lower electrode material (the polycrystalline silicon film) of the substrate to lower the effective dielectric constant of the capacitor insulating film. Another problem is that the oxygen in the tantalum oxide film becomes scarce to resulting in a lower breakdown voltage of the film, thereby to increase the leakage current.
Japanese Patent Laid-Open No. 3548/1986 has disclosed a technique for correcting this defect due to the oxygen vacancy in the tantalum oxide film deposited over a semiconductor substrate using the CVD method, thereby to improve the insulating breakdown voltage of the film by annealing the surface of the film in the atmosphere of dry oxygen.
"International Conference on Solidstate Devices and Materials 1992" (pp. 521 to 523) has disclosed a technique for preventing an oxide film from being formed on the surface of a polycrystalline silicon film constituting a lower electrode of a capacitive element, when a tantalum oxide film is to be deposited, by annealing the polycrystalline silicon film in the atmosphere of NH.sub.3 (ammonia) to form a nitride film on the surface of the polycrystalline silicon film.
In the DRAM disclosed in Japanese Patent Laid-Open No. 66300/1995, the capacitor insulating film of the capacitive element is made of tantalum oxide, strontium titanate (SrTiO.sub.3) or barium titanate deposited by the CVD method, and the upper electrode is made of W, Pt or TiN deposited by the CVD method or the sputtering method. Moreover, the lower electrode is made of a material such as zinc oxide (ZnO) or tin oxide (SnO.sub.2) exhibiting a high resistance to oxidation, so that any oxidized film is prevented from being formed at the interface with the lower electrode at the time of annealing the capacitor insulating film.
In the DRAM disclosed in Japanese Patent Laid-Open No. 66369/1995, the capacitor insulating film of a capacitive element is made of tantalum oxide deposited by the CVD method. By annealing the formed film at a lower temperature (lower than about 600.degree. C.) than that for crystallization, thereby to hold the film in an amorphous structure, moreover, the occurrence of a grain boundary, cracking or a micro defect which might establish paths for the leakage current is suppressed so as to improve the leakage current characteristics.
In the DRAM disclosed in Japanese Patent Laid-Open No. 222469/1989, the capacitor insulating film of a capacitive element is made of tantalum oxide or hafnium oxide (HfO.sub.2) deposited by the CVD method, and a barrier film of TiN is formed between the tantalum oxide (or hafnium oxide) and the electrodes (the upper electrode and the lower electrode) of polycrystalline silicon thereby to prevent a reaction between the silicon and the tantalum oxide.
In the DRAM disclosed in Japanese Patent Laid-Open No. 232344/1994, the capacitor insulating film of a capacitive element is made of tantalum oxide or hafnium oxide deposited by the CVD method, and the upper electrode is made of TiN. By forming a nonmetal buffering film of polycrystalline silicon over the TiN, the capacitive element is prevented from deteriorating when a BPSG (Boron-doped Phospho Silicate Glass) film deposited over the capacitive element is subjected to hot reflow (at about 850.degree. C. for 30 minutes).